1. Field
This disclosure relates generally to an integrated circuit and, more specifically, to techniques for reducing power requirements of an integrated circuit.
2. Related Art
As technologies become have become more bounded by packaging and applications, increased power requirements have become a problem for designers of complex very large scale integrated (VLSI) chips. To meet performance demands, designers have (in many cases) increased a clock frequency of a chip and/or increased design complexity of the chip. However, as clock frequency and complexity of chip designs have increased, power requirements have also generally increased. Unfortunately, many popular applications (such as hand-held devices like personal digital assistants (PDAs), cellular telephones, MP3 players, etc., that are battery-powered) require low-power operation. As a result, designers are faced with goals that are usually mutually exclusive, i.e., increase performance (which usually requires increased complexity and/or increased clock speed) of a chip while reducing power requirements of the chip.
There are various conventional approaches that have been implemented to reduce power dissipation of a chip. For example, at least some chip designs have limited a clock frequency of a chip. Others chip designs have employed low-power circuitry, which tends to be slower in operation (which limits a maximum clock frequency that can be used to clock a chip). Still other chip designs have employed power throttling techniques to reduce power dissipation of a chip by selectively deactivating portions of the chip that are not used and/or are consuming significant amounts of power. For example, U.S. Pat. No. 6,785,826 (hereinafter the '826 patent) describes a technique for throttling chip partitions based on measured local power dissipation. Another power throttling technique compares input and output states of a given register and selectively gates a corresponding clock signal based on the states of the register.